Soldered SD Card Arduino Library 1.0.0
Easily read and write files to and form the SD card breakout! A fork of the original SDFat library by Bill Greiman.
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SdioTeensy.h
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1#ifndef SdioTeensy_h
2#define SdioTeensy_h
3
4// From Paul's SD.h driver.
5
6#if defined(__IMXRT1062__)
7#define MAKE_REG_MASK(m, s) (((uint32_t)(((uint32_t)(m) << s))))
8#define MAKE_REG_GET(x, m, s) (((uint32_t)(((uint32_t)(x) >> s) & m)))
9#define MAKE_REG_SET(x, m, s) (((uint32_t)(((uint32_t)(x)&m) << s)))
10
11#define SDHC_BLKATTR_BLKSIZE_MASK MAKE_REG_MASK(0x1FFF, 0) // uint32_t)(((n) & 0x1FFF)<<0) // Transfer Block Size Mask
12#define SDHC_BLKATTR_BLKSIZE(n) MAKE_REG_SET(n, 0x1FFF, 0) // uint32_t)(((n) & 0x1FFF)<<0) // Transfer Block Size
13#define SDHC_BLKATTR_BLKCNT_MASK MAKE_REG_MASK(0x1FFF, 16) //((uint32_t)0x1FFF<<16)
14#define SDHC_BLKATTR_BLKCNT(n) \
15 MAKE_REG_SET(n, 0x1FFF, 16) //(uint32_t)(((n) & 0x1FFF)<<16) // Blocks Count For Current Transfer
16
17#define SDHC_XFERTYP_CMDINX(n) MAKE_REG_SET(n, 0x3F, 24) //(uint32_t)(((n) & 0x3F)<<24)// Command Index
18#define SDHC_XFERTYP_CMDTYP(n) MAKE_REG_SET(n, 0x3, 22) //(uint32_t)(((n) & 0x3)<<22) // Command Type
19#define SDHC_XFERTYP_DPSEL MAKE_REG_MASK(0x1, 21) //((uint32_t)0x00200000) // Data Present Select
20#define SDHC_XFERTYP_CICEN MAKE_REG_MASK(0x1, 20) //((uint32_t)0x00100000) // Command Index Check Enable
21#define SDHC_XFERTYP_CCCEN MAKE_REG_MASK(0x1, 19) //((uint32_t)0x00080000) // Command CRC Check Enable
22#define SDHC_XFERTYP_RSPTYP(n) MAKE_REG_SET(n, 0x3, 16) //(uint32_t)(((n) & 0x3)<<16) // Response Type Select
23#define SDHC_XFERTYP_MSBSEL MAKE_REG_MASK(0x1, 5) //((uint32_t)0x00000020) // Multi/Single Block Select
24#define SDHC_XFERTYP_DTDSEL MAKE_REG_MASK(0x1, 4) //((uint32_t)0x00000010) // Data Transfer Direction Select
25#define SDHC_XFERTYP_AC12EN MAKE_REG_MASK(0x1, 2) //((uint32_t)0x00000004) // Auto CMD12 Enable
26#define SDHC_XFERTYP_BCEN MAKE_REG_MASK(0x1, 1) //((uint32_t)0x00000002) // Block Count Enable
27#define SDHC_XFERTYP_DMAEN MAKE_REG_MASK(0x3, 0) //((uint32_t)0x00000001) // DMA Enable
28
29#define SDHC_PRSSTAT_DLSL_MASK MAKE_REG_MASK(0xFF, 24) //((uint32_t)0xFF000000) // DAT Line Signal Level
30#define SDHC_PRSSTAT_CLSL MAKE_REG_MASK(0x1, 23) //((uint32_t)0x00800000) // CMD Line Signal Level
31#define SDHC_PRSSTAT_WPSPL MAKE_REG_MASK(0x1, 19) //
32#define SDHC_PRSSTAT_CDPL MAKE_REG_MASK(0x1, 18) //
33#define SDHC_PRSSTAT_CINS MAKE_REG_MASK(0x1, 16) //((uint32_t)0x00010000) // Card Inserted
34#define SDHC_PRSSTAT_TSCD MAKE_REG_MASK(0x1, 15)
35#define SDHC_PRSSTAT_RTR MAKE_REG_MASK(0x1, 12)
36#define SDHC_PRSSTAT_BREN MAKE_REG_MASK(0x1, 11) //((uint32_t)0x00000800) // Buffer Read Enable
37#define SDHC_PRSSTAT_BWEN MAKE_REG_MASK(0x1, 10) //((uint32_t)0x00000400) // Buffer Write Enable
38#define SDHC_PRSSTAT_RTA MAKE_REG_MASK(0x1, 9) //((uint32_t)0x00000200) // Read Transfer Active
39#define SDHC_PRSSTAT_WTA MAKE_REG_MASK(0x1, 8) //((uint32_t)0x00000100) // Write Transfer Active
40#define SDHC_PRSSTAT_SDOFF MAKE_REG_MASK(0x1, 7) //((uint32_t)0x00000080) // SD Clock Gated Off Internally
41#define SDHC_PRSSTAT_PEROFF MAKE_REG_MASK(0x1, 6) //((uint32_t)0x00000040) // SDHC clock Gated Off Internally
42#define SDHC_PRSSTAT_HCKOFF MAKE_REG_MASK(0x1, 5) //((uint32_t)0x00000020) // System Clock Gated Off Internally
43#define SDHC_PRSSTAT_IPGOFF MAKE_REG_MASK(0x1, 4) //((uint32_t)0x00000010) // Bus Clock Gated Off Internally
44#define SDHC_PRSSTAT_SDSTB MAKE_REG_MASK(0x1, 3) //((uint32_t)0x00000008) // SD Clock Stable
45#define SDHC_PRSSTAT_DLA MAKE_REG_MASK(0x1, 2) //((uint32_t)0x00000004) // Data Line Active
46#define SDHC_PRSSTAT_CDIHB MAKE_REG_MASK(0x1, 1) //((uint32_t)0x00000002) // Command Inhibit (DAT)
47#define SDHC_PRSSTAT_CIHB MAKE_REG_MASK(0x1, 0) //((uint32_t)0x00000001) // Command Inhibit (CMD)
48
49#define SDHC_PROTCT_NONEXACT_BLKRD MAKE_REG_MASK(0x1, 30) //
50#define SDHC_PROTCT_BURST_LENEN(n) MAKE_REG_SET(n, 0x7, 12) //
51#define SDHC_PROCTL_WECRM MAKE_REG_MASK(0x1, 26) //((uint32_t)0x04000000) // Wakeup Event Enable On SD Card Removal
52#define SDHC_PROCTL_WECINS \
53 MAKE_REG_MASK(0x1, 25) //((uint32_t)0x02000000) // Wakeup Event Enable On SD Card Insertion
54#define SDHC_PROCTL_WECINT MAKE_REG_MASK(0x1, 24) //((uint32_t)0x01000000) // Wakeup Event Enable On Card Interrupt
55#define SDHC_PROCTL_RD_DONE_NOBLK MAKE_REG_MASK(0x1, 20) //
56#define SDHC_PROCTL_IABG MAKE_REG_MASK(0x1, 19) //((uint32_t)0x00080000) // Interrupt At Block Gap
57#define SDHC_PROCTL_RWCTL MAKE_REG_MASK(0x1, 18) //((uint32_t)0x00040000) // Read Wait Control
58#define SDHC_PROCTL_CREQ MAKE_REG_MASK(0x1, 17) //((uint32_t)0x00020000) // Continue Request
59#define SDHC_PROCTL_SABGREQ MAKE_REG_MASK(0x1, 16) //((uint32_t)0x00010000) // Stop At Block Gap Request
60#define SDHC_PROCTL_DMAS(n) MAKE_REG_SET(n, 0x3, 8) //(uint32_t)(((n) & 0x3)<<8) // DMA Select
61#define SDHC_PROCTL_CDSS MAKE_REG_MASK(0x1, 7) //((uint32_t)0x00000080) // Card Detect Signal Selection
62#define SDHC_PROCTL_CDTL MAKE_REG_MASK(0x1, 6) //((uint32_t)0x00000040) // Card Detect Test Level
63#define SDHC_PROCTL_EMODE(n) MAKE_REG_SET(n, 0x3, 4) //(uint32_t)(((n) & 0x3)<<4) // Endian Mode
64#define SDHC_PROCTL_EMODE_MASK MAKE_REG_MASK(0x3, 4) //(uint32_t)((0x3)<<4) // Endian Mode
65#define SDHC_PROCTL_D3CD MAKE_REG_MASK(0x1, 3) //((uint32_t)0x00000008) // DAT3 As Card Detection Pin
66#define SDHC_PROCTL_DTW(n) \
67 MAKE_REG_SET(n, 0x3, 1) //(uint32_t)(((n) & 0x3)<<1) // Data Transfer Width, 0=1bit, 1=4bit, 2=8bit
68#define SDHC_PROCTL_DTW_MASK MAKE_REG_MASK(0x3, 1) //((uint32_t)0x00000006)
69#define SDHC_PROCTL_LCTL MAKE_REG_MASK(0x1, 0) //((uint32_t)0x00000001) // LED Control
70
71#define SDHC_SYSCTL_RSTT MAKE_REG_MASK(0x1, 28) //
72#define SDHC_SYSCTL_INITA MAKE_REG_MASK(0x1, 27) //((uint32_t)0x08000000) // Initialization Active
73#define SDHC_SYSCTL_RSTD MAKE_REG_MASK(0x1, 26) //((uint32_t)0x04000000) // Software Reset For DAT Line
74#define SDHC_SYSCTL_RSTC MAKE_REG_MASK(0x1, 25) //((uint32_t)0x02000000) // Software Reset For CMD Line
75#define SDHC_SYSCTL_RSTA MAKE_REG_MASK(0x1, 24) //((uint32_t)0x01000000) // Software Reset For ALL
76#define SDHC_SYSCTL_DTOCV(n) MAKE_REG_SET(n, 0xF, 16) //(uint32_t)(((n) & 0xF)<<16) // Data Timeout Counter Value
77#define SDHC_SYSCTL_DTOCV_MASK MAKE_REG_MASK(0xF, 16) //((uint32_t)0x000F0000)
78#define SDHC_SYSCTL_SDCLKFS(n) MAKE_REG_SET(n, 0xFF, 8) //(uint32_t)(((n) & 0xFF)<<8) // SDCLK Frequency Select
79#define SDHC_SYSCTL_SDCLKFS_MASK MAKE_REG_MASK(0xFF, 8) //((uint32_t)0x0000FF00)
80#define SDHC_SYSCTL_DVS(n) MAKE_REG_SET(n, 0xF, 4) //(uint32_t)(((n) & 0xF)<<4) // Divisor
81#define SDHC_SYSCTL_DVS_MASK MAKE_REG_MASK(0xF, 4) //((uint32_t)0x000000F0)
82
83#define SDHC_SYSCTL_SDCLKEN ((uint32_t)0x00000008) // SD Clock Enable
84#define SDHC_SYSCTL_PEREN ((uint32_t)0x00000004) // Peripheral Clock Enable
85#define SDHC_SYSCTL_HCKEN ((uint32_t)0x00000002) // System Clock Enable
86#define SDHC_SYSCTL_IPGEN ((uint32_t)0x00000001) // IPG Clock Enable
87
88#define SDHC_IRQSTAT_DMAE MAKE_REG_MASK(0x1, 28) //((uint32_t)0x10000000) // DMA Error
89#define SDHC_IRQSTAT_TNE MAKE_REG_MASK(0x1, 26) //
90#define SDHC_IRQSTAT_AC12E MAKE_REG_MASK(0x1, 24) //((uint32_t)0x01000000) // Auto CMD12 Error
91#define SDHC_IRQSTAT_DEBE MAKE_REG_MASK(0x1, 22) //((uint32_t)0x00400000) // Data End Bit Error
92#define SDHC_IRQSTAT_DCE MAKE_REG_MASK(0x1, 21) //((uint32_t)0x00200000) // Data CRC Error
93#define SDHC_IRQSTAT_DTOE MAKE_REG_MASK(0x1, 20) //((uint32_t)0x00100000) // Data Timeout Error
94#define SDHC_IRQSTAT_CIE MAKE_REG_MASK(0x1, 19) //((uint32_t)0x00080000) // Command Index Error
95#define SDHC_IRQSTAT_CEBE MAKE_REG_MASK(0x1, 18) //((uint32_t)0x00040000) // Command End Bit Error
96#define SDHC_IRQSTAT_CCE MAKE_REG_MASK(0x1, 17) //((uint32_t)0x00020000) // Command CRC Error
97#define SDHC_IRQSTAT_CTOE MAKE_REG_MASK(0x1, 16) //((uint32_t)0x00010000) // Command Timeout Error
98#define SDHC_IRQSTAT_TP MAKE_REG_MASK(0x1, 14) //
99#define SDHC_IRQSTAT_RTE MAKE_REG_MASK(0x1, 12) //
100#define SDHC_IRQSTAT_CINT MAKE_REG_MASK(0x1, 8) //((uint32_t)0x00000100) // Card Interrupt
101#define SDHC_IRQSTAT_CRM MAKE_REG_MASK(0x1, 7) //((uint32_t)0x00000080) // Card Removal
102#define SDHC_IRQSTAT_CINS MAKE_REG_MASK(0x1, 6) //((uint32_t)0x00000040) // Card Insertion
103#define SDHC_IRQSTAT_BRR MAKE_REG_MASK(0x1, 5) //((uint32_t)0x00000020) // Buffer Read Ready
104#define SDHC_IRQSTAT_BWR MAKE_REG_MASK(0x1, 4) //((uint32_t)0x00000010) // Buffer Write Ready
105#define SDHC_IRQSTAT_DINT MAKE_REG_MASK(0x1, 3) //((uint32_t)0x00000008) // DMA Interrupt
106#define SDHC_IRQSTAT_BGE MAKE_REG_MASK(0x1, 2) //((uint32_t)0x00000004) // Block Gap Event
107#define SDHC_IRQSTAT_TC MAKE_REG_MASK(0x1, 1) //((uint32_t)0x00000002) // Transfer Complete
108#define SDHC_IRQSTAT_CC MAKE_REG_MASK(0x1, 0) //((uint32_t)0x00000001) // Command Complete
109
110#define SDHC_IRQSTATEN_DMAESEN MAKE_REG_MASK(0x1, 28) //((uint32_t)0x10000000) // DMA Error Status Enable
111#define SDHC_IRQSTATEN_TNESEN MAKE_REG_MASK(0x1, 26) //
112#define SDHC_IRQSTATEN_AC12ESEN MAKE_REG_MASK(0x1, 24) //((uint32_t)0x01000000) // Auto CMD12 Error Status Enable
113#define SDHC_IRQSTATEN_DEBESEN MAKE_REG_MASK(0x1, 22) //((uint32_t)0x00400000) // Data End Bit Error Status Enable
114#define SDHC_IRQSTATEN_DCESEN MAKE_REG_MASK(0x1, 21) //((uint32_t)0x00200000) // Data CRC Error Status Enable
115#define SDHC_IRQSTATEN_DTOESEN MAKE_REG_MASK(0x1, 20) //((uint32_t)0x00100000) // Data Timeout Error Status Enable
116#define SDHC_IRQSTATEN_CIESEN MAKE_REG_MASK(0x1, 19) //((uint32_t)0x00080000) // Command Index Error Status Enable
117#define SDHC_IRQSTATEN_CEBESEN MAKE_REG_MASK(0x1, 18) //((uint32_t)0x00040000) // Command End Bit Error Status Enable
118#define SDHC_IRQSTATEN_CCESEN MAKE_REG_MASK(0x1, 17) //((uint32_t)0x00020000) // Command CRC Error Status Enable
119#define SDHC_IRQSTATEN_CTOESEN MAKE_REG_MASK(0x1, 16) //((uint32_t)0x00010000) // Command Timeout Error Status Enable
120#define SDHC_IRQSTATEN_TPSEN MAKE_REG_MASK(0x1, 14) //
121#define SDHC_IRQSTATEN_RTESEN MAKE_REG_MASK(0x1, 12) //
122#define SDHC_IRQSTATEN_CINTSEN MAKE_REG_MASK(0x1, 8) //((uint32_t)0x00000100) // Card Interrupt Status Enable
123#define SDHC_IRQSTATEN_CRMSEN MAKE_REG_MASK(0x1, 7) //((uint32_t)0x00000080) // Card Removal Status Enable
124#define SDHC_IRQSTATEN_CINSEN MAKE_REG_MASK(0x1, 6) //((uint32_t)0x00000040) // Card Insertion Status Enable
125#define SDHC_IRQSTATEN_BRRSEN MAKE_REG_MASK(0x1, 5) //((uint32_t)0x00000020) // Buffer Read Ready Status Enable
126#define SDHC_IRQSTATEN_BWRSEN MAKE_REG_MASK(0x1, 4) //((uint32_t)0x00000010) // Buffer Write Ready Status Enable
127#define SDHC_IRQSTATEN_DINTSEN MAKE_REG_MASK(0x1, 3) //((uint32_t)0x00000008) // DMA Interrupt Status Enable
128#define SDHC_IRQSTATEN_BGESEN MAKE_REG_MASK(0x1, 2) //((uint32_t)0x00000004) // Block Gap Event Status Enable
129#define SDHC_IRQSTATEN_TCSEN MAKE_REG_MASK(0x1, 1) //((uint32_t)0x00000002) // Transfer Complete Status Enable
130#define SDHC_IRQSTATEN_CCSEN MAKE_REG_MASK(0x1, 0) //((uint32_t)0x00000001) // Command Complete Status Enable
131
132#define SDHC_IRQSIGEN_DMAEIEN MAKE_REG_MASK(0x1, 28) //((uint32_t)0x10000000) // DMA Error Interrupt Enable
133#define SDHC_IRQSIGEN_TNEIEN MAKE_REG_MASK(0x1, 26) //
134#define SDHC_IRQSIGEN_AC12EIEN MAKE_REG_MASK(0x1, 24) //((uint32_t)0x01000000) // Auto CMD12 Error Interrupt Enable
135#define SDHC_IRQSIGEN_DEBEIEN MAKE_REG_MASK(0x1, 22) //((uint32_t)0x00400000) // Data End Bit Error Interrupt Enable
136#define SDHC_IRQSIGEN_DCEIEN MAKE_REG_MASK(0x1, 21) //((uint32_t)0x00200000) // Data CRC Error Interrupt Enable
137#define SDHC_IRQSIGEN_DTOEIEN MAKE_REG_MASK(0x1, 20) //((uint32_t)0x00100000) // Data Timeout Error Interrupt Enable
138#define SDHC_IRQSIGEN_CIEIEN MAKE_REG_MASK(0x1, 19) //((uint32_t)0x00080000) // Command Index Error Interrupt Enable
139#define SDHC_IRQSIGEN_CEBEIEN \
140 MAKE_REG_MASK(0x1, 18) //((uint32_t)0x00040000) // Command End Bit Error Interrupt Enable
141#define SDHC_IRQSIGEN_CCEIEN MAKE_REG_MASK(0x1, 17) //((uint32_t)0x00020000) // Command CRC Error Interrupt Enable
142#define SDHC_IRQSIGEN_CTOEIEN \
143 MAKE_REG_MASK(0x1, 16) //((uint32_t)0x00010000) // Command Timeout Error Interrupt Enable
144#define SDHC_IRQSIGEN_TPIEN MAKE_REG_MASK(0x1, 14) //
145#define SDHC_IRQSIGEN_RTEIEN MAKE_REG_MASK(0x1, 12) //
146#define SDHC_IRQSIGEN_CINTIEN MAKE_REG_MASK(0x1, 8) //((uint32_t)0x00000100) // Card Interrupt Interrupt Enable
147#define SDHC_IRQSIGEN_CRMIEN MAKE_REG_MASK(0x1, 7) //((uint32_t)0x00000080) // Card Removal Interrupt Enable
148#define SDHC_IRQSIGEN_CINSIEN MAKE_REG_MASK(0x1, 6) //((uint32_t)0x00000040) // Card Insertion Interrupt Enable
149#define SDHC_IRQSIGEN_BRRIEN MAKE_REG_MASK(0x1, 5) //((uint32_t)0x00000020) // Buffer Read Ready Interrupt Enable
150#define SDHC_IRQSIGEN_BWRIEN MAKE_REG_MASK(0x1, 4) //((uint32_t)0x00000010) // Buffer Write Ready Interrupt Enable
151#define SDHC_IRQSIGEN_DINTIEN MAKE_REG_MASK(0x1, 3) //((uint32_t)0x00000008) // DMA Interrupt Interrupt Enable
152#define SDHC_IRQSIGEN_BGEIEN MAKE_REG_MASK(0x1, 2) //((uint32_t)0x00000004) // Block Gap Event Interrupt Enable
153#define SDHC_IRQSIGEN_TCIEN MAKE_REG_MASK(0x1, 1) //((uint32_t)0x00000002) // Transfer Complete Interrupt Enable
154#define SDHC_IRQSIGEN_CCIEN MAKE_REG_MASK(0x1, 0) //((uint32_t)0x00000001) // Command Complete Interrupt Enable
155
156#define SDHC_AC12ERR_SMPLCLK_SEL MAKE_REG_MASK(0x1, 23) //
157#define SDHC_AC12ERR_EXEC_TUNING MAKE_REG_MASK(0x1, 22) //
158#define SDHC_AC12ERR_CNIBAC12E \
159 MAKE_REG_MASK(0x1, 7) //((uint32_t)0x00000080) // Command Not Issued By Auto CMD12 Error
160#define SDHC_AC12ERR_AC12IE MAKE_REG_MASK(0x1, 4) //((uint32_t)0x00000010) // Auto CMD12 Index Error
161#define SDHC_AC12ERR_AC12CE MAKE_REG_MASK(0x1, 3) //((uint32_t)0x00000008) // Auto CMD12 CRC Error
162#define SDHC_AC12ERR_AC12EBE MAKE_REG_MASK(0x1, 2) //((uint32_t)0x00000004) // Auto CMD12 End Bit Error
163#define SDHC_AC12ERR_AC12TOE MAKE_REG_MASK(0x1, 1) //((uint32_t)0x00000002) // Auto CMD12 Timeout Error
164#define SDHC_AC12ERR_AC12NE MAKE_REG_MASK(0x1, 0) //((uint32_t)0x00000001) // Auto CMD12 Not Executed
165
166#define SDHC_HTCAPBLT_VS18 MAKE_REG_MASK(0x1, 26) //
167#define SDHC_HTCAPBLT_VS30 MAKE_REG_MASK(0x1, 25) //
168#define SDHC_HTCAPBLT_VS33 MAKE_REG_MASK(0x1, 24) //
169#define SDHC_HTCAPBLT_SRS MAKE_REG_MASK(0x1, 23) //
170#define SDHC_HTCAPBLT_DMAS MAKE_REG_MASK(0x1, 22) //
171#define SDHC_HTCAPBLT_HSS MAKE_REG_MASK(0x1, 21) //
172#define SDHC_HTCAPBLT_ADMAS MAKE_REG_MASK(0x1, 20) //
173#define SDHC_HTCAPBLT_MBL_VAL MAKE_REG_GET((USDHC1_HOST_CTRL_CAP), 0x7, 16) //
174#define SDHC_HTCAPBLT_RETUN_MODE MAKE_REG_GET((USDHC1_HOST_CTRL_CAP), 0x3, 14) //
175#define SDHC_HTCAPBLT_TUNE_SDR50 MAKE_REG_MASK(0x1, 13) //
176#define SDHC_HTCAPBLT_TIME_RETUN(n) MAKE_REG_SET(n, 0xF, 8) //
177
178#define SDHC_WML_WR_BRSTLEN_MASK MAKE_REG_MASK(0x1F, 24) //
179#define SDHC_WML_RD_BRSTLEN_MASK MAKE_REG_MASK(0x1F, 8) //
180#define SDHC_WML_WR_WML_MASK MAKE_REG_MASK(0xFF, 16) //
181#define SDHC_WML_RD_WML_MASK MAKE_REG_MASK(0xFF, 0) //
182#define SDHC_WML_WR_BRSTLEN(n) MAKE_REG_SET(n, 0x1F, 24) //(uint32_t)(((n) & 0x7F)<<16) // Write Burst Len
183#define SDHC_WML_RD_BRSTLEN(n) MAKE_REG_SET(n, 0x1F, 8) //(uint32_t)(((n) & 0x7F)<<0) // Read Burst Len
184#define SDHC_WML_WR_WML(n) MAKE_REG_SET(n, 0xFF, 16) //(uint32_t)(((n) & 0x7F)<<16) // Write Watermark Level
185#define SDHC_WML_RD_WML(n) MAKE_REG_SET(n, 0xFF, 0) //(uint32_t)(((n) & 0x7F)<<0) // Read Watermark Level
186#define SDHC_WML_WRWML(n) MAKE_REG_SET(n, 0xFF, 16) //(uint32_t)(((n) & 0x7F)<<16) // Write Watermark Level
187#define SDHC_WML_RDWML(n) MAKE_REG_SET(n, 0xFF, 0) //(uint32_t)(((n) & 0x7F)<<0) // Read Watermark Level
188
189// Teensy 4.0 only
190#define SDHC_MIX_CTRL_DMAEN MAKE_REG_MASK(0x1, 0) //
191#define SDHC_MIX_CTRL_BCEN MAKE_REG_MASK(0x1, 1) //
192#define SDHC_MIX_CTRL_AC12EN MAKE_REG_MASK(0x1, 2) //
193#define SDHC_MIX_CTRL_DDR_EN MAKE_REG_MASK(0x1, 3) //
194#define SDHC_MIX_CTRL_DTDSEL MAKE_REG_MASK(0x1, 4) //
195#define SDHC_MIX_CTRL_MSBSEL MAKE_REG_MASK(0x1, 5) //
196#define SDHC_MIX_CTRL_NIBBLE_POS MAKE_REG_MASK(0x1, 6) //
197#define SDHC_MIX_CTRL_AC23EN MAKE_REG_MASK(0x1, 7) //
198
199#define SDHC_FEVT_CINT MAKE_REG_MASK(0x1, 31) //((uint32_t)0x80000000) // Force Event Card Interrupt
200#define SDHC_FEVT_DMAE MAKE_REG_MASK(0x1, 28) //((uint32_t)0x10000000) // Force Event DMA Error
201#define SDHC_FEVT_AC12E MAKE_REG_MASK(0x1, 24) //((uint32_t)0x01000000) // Force Event Auto CMD12 Error
202#define SDHC_FEVT_DEBE MAKE_REG_MASK(0x1, 22) //((uint32_t)0x00400000) // Force Event Data End Bit Error
203#define SDHC_FEVT_DCE MAKE_REG_MASK(0x1, 21) //((uint32_t)0x00200000) // Force Event Data CRC Error
204#define SDHC_FEVT_DTOE MAKE_REG_MASK(0x1, 20) //((uint32_t)0x00100000) // Force Event Data Timeout Error
205#define SDHC_FEVT_CIE MAKE_REG_MASK(0x1, 19) //((uint32_t)0x00080000) // Force Event Command Index Error
206#define SDHC_FEVT_CEBE MAKE_REG_MASK(0x1, 18) //((uint32_t)0x00040000) // Force Event Command End Bit Error
207#define SDHC_FEVT_CCE MAKE_REG_MASK(0x1, 17) //((uint32_t)0x00020000) // Force Event Command CRC Error
208#define SDHC_FEVT_CTOE MAKE_REG_MASK(0x1, 16) //((uint32_t)0x00010000) // Force Event Command Timeout Error
209#define SDHC_FEVT_CNIBAC12E \
210 MAKE_REG_MASK(0x1, 7) //((uint32_t)0x00000080) // Force Event Command Not Executed By Auto Command 12 Error
211#define SDHC_FEVT_AC12IE MAKE_REG_MASK(0x1, 4) //((uint32_t)0x00000010) // Force Event Auto Command 12 Index Error
212#define SDHC_FEVT_AC12EBE MAKE_REG_MASK(0x1, 3) //((uint32_t)0x00000008) // Force Event Auto Command 12 End Bit Error
213#define SDHC_FEVT_AC12CE MAKE_REG_MASK(0x1, 2) //((uint32_t)0x00000004) // Force Event Auto Command 12 CRC Error
214#define SDHC_FEVT_AC12TOE \
215 MAKE_REG_MASK(0x1, 1) //((uint32_t)0x00000002) // Force Event Auto Command 12 Time Out Error
216#define SDHC_FEVT_AC12NE MAKE_REG_MASK(0x1, 0) //((uint32_t)0x00000001) // Force Event Auto Command 12 Not Executed
217
218#define SDHC_ADMAES_ADMADCE MAKE_REG_MASK(0x1, 3) //((uint32_t)0x00000008)
219#define SDHC_ADMAES_ADMALME MAKE_REG_MASK(0x1, 2) //((uint32_t)0x00000004)
220#define SDHC_ADMAES_ADMAES_MASK MAKE_REG_MASK(0x3, 0) //((uint32_t)0x00000003)
221
222#define SDHC_MMCBOOT_BOOTBLKCNT(n) \
223 MAKE_REG_MASK(0xFF, 16) //(uint32_t)(((n) & 0xFFF)<<16) // stop at block gap value of automatic mode
224#define SDHC_MMCBOOT_AUTOSABGEN \
225 MAKE_REG_MASK(0x1, 7) //((uint32_t)0x00000080) // enable auto stop at block gap function
226#define SDHC_MMCBOOT_BOOTEN MAKE_REG_MASK(0x1, 6) //((uint32_t)0x00000040) // Boot Mode Enable
227#define SDHC_MMCBOOT_BOOTMODE MAKE_REG_MASK(0x1, 5) //((uint32_t)0x00000020) // Boot Mode Select
228#define SDHC_MMCBOOT_BOOTACK MAKE_REG_MASK(0x1, 4) //((uint32_t)0x00000010) // Boot Ack Mode Select
229#define SDHC_MMCBOOT_DTOCVACK(n) MAKE_REG_MASK(0xF, 0) //(uint32_t)(((n) & 0xF)<<0) // Boot ACK Time Out Counter Value
230//#define SDHC_HOSTVER (*(volatile uint32_t*)0x400B10FC) // Host Controller Version
231
232#define CCM_ANALOG_PFD_528_PFD0_FRAC_MASK 0x3f
233#define CCM_ANALOG_PFD_528_PFD0_FRAC(n) ((n)&CCM_ANALOG_PFD_528_PFD0_FRAC_MASK)
234#define CCM_ANALOG_PFD_528_PFD1_FRAC_MASK (0x3f << 8)
235#define CCM_ANALOG_PFD_528_PFD1_FRAC(n) (((n) << 8) & CCM_ANALOG_PFD_528_PFD1_FRAC_MASK)
236#define CCM_ANALOG_PFD_528_PFD2_FRAC_MASK (0x3f << 16)
237#define CCM_ANALOG_PFD_528_PFD2_FRAC(n) (((n) << 16) & CCM_ANALOG_PFD_528_PFD2_FRAC_MASK)
238#define CCM_ANALOG_PFD_528_PFD3_FRAC_MASK ((0x3f<<24)
239#define CCM_ANALOG_PFD_528_PFD3_FRAC(n) (((n) << 24) & CCM_ANALOG_PFD_528_PFD3_FRAC_MASK)
240
241#define SDHC_DSADDR (USDHC1_DS_ADDR) // DMA System Address register
242#define SDHC_BLKATTR (USDHC1_BLK_ATT) // Block Attributes register
243#define SDHC_CMDARG (USDHC1_CMD_ARG) // Command Argument register
244#define SDHC_XFERTYP (USDHC1_CMD_XFR_TYP) // Transfer Type register
245#define SDHC_CMDRSP0 (USDHC1_CMD_RSP0) // Command Response 0
246#define SDHC_CMDRSP1 (USDHC1_CMD_RSP1) // Command Response 1
247#define SDHC_CMDRSP2 (USDHC1_CMD_RSP2) // Command Response 2
248#define SDHC_CMDRSP3 (USDHC1_CMD_RSP3) // Command Response 3
249#define SDHC_DATPORT (USDHC1_DATA_BUFF_ACC_PORT) // Buffer Data Port register
250#define SDHC_PRSSTAT (USDHC1_PRES_STATE) // Present State register
251#define SDHC_PROCTL (USDHC1_PROT_CTRL) // Protocol Control register
252#define SDHC_SYSCTL (USDHC1_SYS_CTRL) // System Control register
253#define SDHC_IRQSTAT (USDHC1_INT_STATUS) // Interrupt Status register
254#define SDHC_IRQSTATEN (USDHC1_INT_STATUS_EN) // Interrupt Status Enable register
255#define SDHC_IRQSIGEN (USDHC1_INT_SIGNAL_EN) // Interrupt Signal Enable register
256#define SDHC_AC12ERR (USDHC1_AUTOCMD12_ERR_STATUS) // Auto CMD12 Error Status Register
257#define SDHC_HTCAPBLT (USDHC1_HOST_CTRL_CAP) // Host Controller Capabilities
258#define SDHC_WML (USDHC1_WTMK_LVL) // Watermark Level Register
259#define SDHC_MIX_CTRL (USDHC1_MIX_CTRL) // Mixer Control
260#define SDHC_FEVT (USDHC1_FORCE_EVENT) // Force Event register
261#define SDHC_ADMAES (USDHC1_ADMA_ERR_STATUS) // ADMA Error Status register
262#define SDHC_ADSADDR (USDHC1_ADMA_SYS_ADDR) // ADMA System Addressregister
263#define SDHC_VENDOR (USDHC1_VEND_SPEC) // Vendor Specific register
264#define SDHC_MMCBOOT (USDHC1_MMC_BOOT) // MMC Boot register
265#define SDHC_VENDOR2 (USDHC2_VEND_SPEC2) // Vendor Specific2 register
266//
267#define IRQ_SDHC IRQ_SDHC1
268
269#define SDHC_MAX_DVS (0xF + 1U)
270#define SDHC_MAX_CLKFS (0xFF + 1U)
271#define SDHC_PREV_DVS(x) ((x) -= 1U)
272#define SDHC_PREV_CLKFS(x, y) ((x) >>= (y))
273
274#define CCM_CSCDR1_USDHC1_CLK_PODF_MASK (0x7 << 11)
275#define CCM_CSCDR1_USDHC1_CLK_PODF(n) (((n)&0x7) << 11)
276
277#define IOMUXC_SW_PAD_CTL_PAD_SRE ((0x1 <) < 0)
278#define IOMUXC_SW_PAD_CTL_PAD_PKE ((0x1) << 12)
279#define IOMUXC_SW_PAD_CTL_PAD_PUE ((0x1) << 13)
280#define IOMUXC_SW_PAD_CTL_PAD_HYS ((0x1) << 16)
281#define IOMUXC_SW_PAD_CTL_PAD_SPEED(n) (((n)&0x3) << 6)
282#define IOMUXC_SW_PAD_CTL_PAD_PUS(n) (((n)&0x3) << 14)
283#define IOMUXC_SW_PAD_CTL_PAD_PUS_MASK ((0x3) << 14)
284#define IOMUXC_SW_PAD_CTL_PAD_DSE(n) (((n)&0x7) << 3)
285#define IOMUXC_SW_PAD_CTL_PAD_DSE_MASK ((0x7) << 3)
286#endif // defined(__IMXRT1062__)
287#endif // SdioTeensy_h