mcp2518fd_can_dfs.h File Reference

Go to the source code of this file.

Classes
struct	_CAN_CONFIG
	CAN Configure. More...
struct	_CAN_TX_FIFO_CONFIG
	CAN Transmit Channel Configure. More...
struct	_CAN_TX_QUEUE_CONFIG
	CAN Transmit Queue Configure. More...
struct	_CAN_RX_FIFO_CONFIG
	CAN Receive Channel Configure. More...
struct	_CAN_TEF_CONFIG
	CAN Transmit Event FIFO Configure. More...
struct	_CAN_MSGOBJ_ID
	CAN Message Object ID. More...
struct	_CAN_TX_MSGOBJ_CTRL
	CAN TX Message Object Control. More...
struct	_CAN_RX_MSGOBJ_CTRL
	CAN RX Message Object Control. More...
union	_CAN_TX_MSGOBJ
	CAN TX Message Object. More...
union	_CAN_RX_MSGOBJ
	CAN RX Message Object. More...
union	_CAN_TEF_MSGOBJ
	CAN TEF Message Object. More...
struct	_CAN_FILTEROBJ_ID
	CAN Filter Object ID. More...
struct	_CAN_MASKOBJ_ID
	CAN Mask Object ID. More...
struct	_CAN_BUS_DIAG_FLAGS
	CAN Bus Diagnostic flags. More...
struct	_CAN_BUS_ERROR_COUNT
	CAN Bus Diagnostic Error Counts. More...
union	_CAN_BUS_DIAGNOSTIC
	CAN BUS DIAGNOSTICS. More...
struct	_CAN_OSC_CTRL
	Oscillator Control. More...
struct	_CAN_OSC_STATUS
	Oscillator Status. More...
union	_REG_t
	General 32-bit Register. More...
union	_REG_CiCON
	CAN Control Register. More...
union	_REG_CiNBTCFG
	Nominal Bit Time Configuration Register. More...
union	_REG_CiDBTCFG
	Data Bit Time Configuration Register. More...
union	_REG_CiTDC
	Transmitter Delay Compensation Register. More...
union	_REG_CiTSCON
	Time Stamp Configuration Register. More...
union	_REG_CiVEC
	Interrupt Vector Register. More...
struct	_CAN_INT_FLAGS
	Interrupt Flags. More...
struct	_CAN_INT_ENABLES
	Interrupt Enables. More...
union	_REG_CiINT
	Interrupt Register. More...
union	_REG_CiINTFLAG
	Interrupt Flag Register. More...
union	_REG_CiINTENABLE
	Interrupt Enable Register. More...
union	_REG_CiTREC
	Transmit/Receive Error Count Register. More...
union	_REG_CiBDIAG0
	Diagnostic Register 0. More...
union	_REG_CiBDIAG1
	Diagnostic Register 1. More...
union	_REG_CiTEFCON
	Transmit Event FIFO Control Register. More...
union	_REG_CiTEFSTA
	Transmit Event FIFO Status Register. More...
union	_REG_CiTXQCON
	Transmit Queue Control Register. More...
union	_REG_CiTXQSTA
	Transmit Queue Status Register. More...
union	_REG_CiFIFOCON
	FIFO Control Register. More...
union	_REG_CiFIFOSTA
	FIFO Status Register. More...
union	_REG_CiFIFOUA
	FIFO User Address Register. More...
union	_REG_CiFLTCON_BYTE
	Filter Control Register. More...
union	_REG_CiFLTOBJ
	Filter Object Register. More...
union	_REG_CiMASK
	Mask Object Register. More...
union	_REG_OSC
	Oscillator Control Register. More...
union	_REG_IOCON
	I/O Control Register. More...
union	_REG_CRC
	CRC Regsiter. More...
union	_REG_ECCCON
	ECC Control Register. More...
union	_REG_ECCSTA
	ECC Status Register. More...
union	_REG_DEVID
	DEVID Register. More...

Typedefs
typedef struct _CAN_CONFIG	CAN_CONFIG
	CAN Configure.
typedef struct _CAN_TX_FIFO_CONFIG	CAN_TX_FIFO_CONFIG
	CAN Transmit Channel Configure.
typedef struct _CAN_TX_QUEUE_CONFIG	CAN_TX_QUEUE_CONFIG
	CAN Transmit Queue Configure.
typedef struct _CAN_RX_FIFO_CONFIG	CAN_RX_FIFO_CONFIG
	CAN Receive Channel Configure.
typedef struct _CAN_TEF_CONFIG	CAN_TEF_CONFIG
	CAN Transmit Event FIFO Configure.
typedef struct _CAN_MSGOBJ_ID	CAN_MSGOBJ_ID
	CAN Message Object ID.
typedef struct _CAN_TX_MSGOBJ_CTRL	CAN_TX_MSGOBJ_CTRL
	CAN TX Message Object Control.
typedef struct _CAN_RX_MSGOBJ_CTRL	CAN_RX_MSGOBJ_CTRL
	CAN RX Message Object Control.
typedef uint32_t	CAN_MSG_TIMESTAMP
	CAN Message Time Stamp.
typedef union _CAN_TX_MSGOBJ	CAN_TX_MSGOBJ
	CAN TX Message Object.
typedef union _CAN_RX_MSGOBJ	CAN_RX_MSGOBJ
	CAN RX Message Object.
typedef union _CAN_TEF_MSGOBJ	CAN_TEF_MSGOBJ
	CAN TEF Message Object.
typedef struct _CAN_FILTEROBJ_ID	CAN_FILTEROBJ_ID
	CAN Filter Object ID.
typedef struct _CAN_MASKOBJ_ID	CAN_MASKOBJ_ID
	CAN Mask Object ID.
typedef struct _CAN_BUS_DIAG_FLAGS	CAN_BUS_DIAG_FLAGS
	CAN Bus Diagnostic flags.
typedef struct _CAN_BUS_ERROR_COUNT	CAN_BUS_ERROR_COUNT
	CAN Bus Diagnostic Error Counts.
typedef union _CAN_BUS_DIAGNOSTIC	CAN_BUS_DIAGNOSTIC
	CAN BUS DIAGNOSTICS.
typedef struct _CAN_OSC_CTRL	CAN_OSC_CTRL
	Oscillator Control.
typedef struct _CAN_OSC_STATUS	CAN_OSC_STATUS
	Oscillator Status.
typedef union _REG_t	REG_t
	General 32-bit Register.
typedef union _REG_CiCON	REG_CiCON
	CAN Control Register.
typedef union _REG_CiNBTCFG	REG_CiNBTCFG
	Nominal Bit Time Configuration Register.
typedef union _REG_CiDBTCFG	REG_CiDBTCFG
	Data Bit Time Configuration Register.
typedef union _REG_CiTDC	REG_CiTDC
	Transmitter Delay Compensation Register.
typedef union _REG_CiTSCON	REG_CiTSCON
	Time Stamp Configuration Register.
typedef union _REG_CiVEC	REG_CiVEC
	Interrupt Vector Register.
typedef struct _CAN_INT_FLAGS	CAN_INT_FLAGS
	Interrupt Flags.
typedef struct _CAN_INT_ENABLES	CAN_INT_ENABLES
	Interrupt Enables.
typedef union _REG_CiINT	REG_CiINT
	Interrupt Register.
typedef union _REG_CiINTFLAG	REG_CiINTFLAG
	Interrupt Flag Register.
typedef union _REG_CiINTENABLE	REG_CiINTENABLE
	Interrupt Enable Register.
typedef union _REG_CiTREC	REG_CiTREC
	Transmit/Receive Error Count Register.
typedef union _REG_CiBDIAG0	REG_CiBDIAG0
	Diagnostic Register 0.
typedef union _REG_CiBDIAG1	REG_CiBDIAG1
	Diagnostic Register 1.
typedef union _REG_CiTEFCON	REG_CiTEFCON
	Transmit Event FIFO Control Register.
typedef union _REG_CiTEFSTA	REG_CiTEFSTA
	Transmit Event FIFO Status Register.
typedef union _REG_CiTXQCON	REG_CiTXQCON
	Transmit Queue Control Register.
typedef union _REG_CiTXQSTA	REG_CiTXQSTA
	Transmit Queue Status Register.
typedef union _REG_CiFIFOCON	REG_CiFIFOCON
	FIFO Control Register.
typedef union _REG_CiFIFOSTA	REG_CiFIFOSTA
	FIFO Status Register.
typedef union _REG_CiFIFOUA	REG_CiFIFOUA
	FIFO User Address Register.
typedef union _REG_CiFLTCON_BYTE	REG_CiFLTCON_BYTE
	Filter Control Register.
typedef union _REG_CiFLTOBJ	REG_CiFLTOBJ
	Filter Object Register.
typedef union _REG_CiMASK	REG_CiMASK
	Mask Object Register.
typedef union _REG_OSC	REG_OSC
	Oscillator Control Register.
typedef union _REG_IOCON	REG_IOCON
	I/O Control Register.
typedef union _REG_CRC	REG_CRC
	CRC Regsiter.
typedef union _REG_ECCCON	REG_ECCCON
	ECC Control Register.
typedef union _REG_ECCSTA	REG_ECCSTA
	ECC Status Register.
typedef union _REG_DEVID	REG_DEVID
	DEVID Register.

Enumerations
enum	CAN_FIFO_CHANNEL {   CAN_FIFO_CH0 , CAN_FIFO_CH1 , CAN_FIFO_CH2 , CAN_FIFO_CH3 ,   CAN_FIFO_CH4 , CAN_FIFO_CH5 , CAN_FIFO_CH6 , CAN_FIFO_CH7 ,   CAN_FIFO_CH8 , CAN_FIFO_CH9 , CAN_FIFO_CH10 , CAN_FIFO_CH11 ,   CAN_FIFO_CH12 , CAN_FIFO_CH13 , CAN_FIFO_CH14 , CAN_FIFO_CH15 ,   CAN_FIFO_CH16 , CAN_FIFO_CH17 , CAN_FIFO_CH18 , CAN_FIFO_CH19 ,   CAN_FIFO_CH20 , CAN_FIFO_CH21 , CAN_FIFO_CH22 , CAN_FIFO_CH23 ,   CAN_FIFO_CH24 , CAN_FIFO_CH25 , CAN_FIFO_CH26 , CAN_FIFO_CH27 ,   CAN_FIFO_CH28 , CAN_FIFO_CH29 , CAN_FIFO_CH30 , CAN_FIFO_CH31 ,   CAN_FIFO_TOTAL_CHANNELS }
	CAN FIFO Channels. More...
enum	CAN_FILTER {   CAN_FILTER0 , CAN_FILTER1 , CAN_FILTER2 , CAN_FILTER3 ,   CAN_FILTER4 , CAN_FILTER5 , CAN_FILTER6 , CAN_FILTER7 ,   CAN_FILTER8 , CAN_FILTER9 , CAN_FILTER10 , CAN_FILTER11 ,   CAN_FILTER12 , CAN_FILTER13 , CAN_FILTER14 , CAN_FILTER15 ,   CAN_FILTER16 , CAN_FILTER17 , CAN_FILTER18 , CAN_FILTER19 ,   CAN_FILTER20 , CAN_FILTER21 , CAN_FILTER22 , CAN_FILTER23 ,   CAN_FILTER24 , CAN_FILTER25 , CAN_FILTER26 , CAN_FILTER27 ,   CAN_FILTER28 , CAN_FILTER29 , CAN_FILTER30 , CAN_FILTER31 ,   CAN_FILTER_TOTAL }
	CAN Filter Channels. More...
enum	CAN_OPERATION_MODE {   CAN_NORMAL_MODE = 0x00 , CAN_SLEEP_MODE = 0x01 , CAN_INTERNAL_LOOPBACK_MODE = 0x02 , CAN_LISTEN_ONLY_MODE = 0x03 ,   CAN_CONFIGURATION_MODE = 0x04 , CAN_EXTERNAL_LOOPBACK_MODE = 0x05 , CAN_CLASSIC_MODE = 0x06 , CAN_RESTRICTED_MODE = 0x07 ,   CAN_INVALID_MODE = 0xFF }
	CAN Operation Modes. More...
enum	CAN_TX_BANDWITH_SHARING {   CAN_TXBWS_NO_DELAY , CAN_TXBWS_2 , CAN_TXBWS_4 , CAN_TXBWS_8 ,   CAN_TXBWS_16 , CAN_TXBWS_32 , CAN_TXBWS_64 , CAN_TXBWS_128 ,   CAN_TXBWS_256 , CAN_TXBWS_512 , CAN_TXBWS_1024 , CAN_TXBWS_2048 ,   CAN_TXBWS_4096 }
	Transmit Bandwidth Sharing. More...
enum	CAN_WAKEUP_FILTER_TIME { CAN_WFT00 , CAN_WFT01 , CAN_WFT10 , CAN_WFT11 }
	Wake-up Filter Time. More...
enum	CAN_DNET_FILTER_SIZE {   CAN_DNET_FILTER_DISABLE = 0 , CAN_DNET_FILTER_SIZE_1_BIT , CAN_DNET_FILTER_SIZE_2_BIT , CAN_DNET_FILTER_SIZE_3_BIT ,   CAN_DNET_FILTER_SIZE_4_BIT , CAN_DNET_FILTER_SIZE_5_BIT , CAN_DNET_FILTER_SIZE_6_BIT , CAN_DNET_FILTER_SIZE_7_BIT ,   CAN_DNET_FILTER_SIZE_8_BIT , CAN_DNET_FILTER_SIZE_9_BIT , CAN_DNET_FILTER_SIZE_10_BIT , CAN_DNET_FILTER_SIZE_11_BIT ,   CAN_DNET_FILTER_SIZE_12_BIT , CAN_DNET_FILTER_SIZE_13_BIT , CAN_DNET_FILTER_SIZE_14_BIT , CAN_DNET_FILTER_SIZE_15_BIT ,   CAN_DNET_FILTER_SIZE_16_BIT , CAN_DNET_FILTER_SIZE_17_BIT , CAN_DNET_FILTER_SIZE_18_BIT }
	Data Byte Filter Number. More...
enum	CAN_FIFO_PLSIZE {   CAN_PLSIZE_8 , CAN_PLSIZE_12 , CAN_PLSIZE_16 , CAN_PLSIZE_20 ,   CAN_PLSIZE_24 , CAN_PLSIZE_32 , CAN_PLSIZE_48 , CAN_PLSIZE_64 }
	FIFO Payload Size. More...
enum	CAN_DLC {   CAN_DLC_0 , CAN_DLC_1 , CAN_DLC_2 , CAN_DLC_3 ,   CAN_DLC_4 , CAN_DLC_5 , CAN_DLC_6 , CAN_DLC_7 ,   CAN_DLC_8 , CAN_DLC_12 , CAN_DLC_16 , CAN_DLC_20 ,   CAN_DLC_24 , CAN_DLC_32 , CAN_DLC_48 , CAN_DLC_64 }
	CAN Data Length Code. More...
enum	CAN_RX_FIFO_STATUS {   CAN_RX_FIFO_EMPTY = 0 , CAN_RX_FIFO_STATUS_MASK = 0x0F , CAN_RX_FIFO_NOT_EMPTY = 0x01 , CAN_RX_FIFO_HALF_FULL = 0x02 ,   CAN_RX_FIFO_FULL = 0x04 , CAN_RX_FIFO_OVERFLOW = 0x08 }
	CAN RX FIFO Status. More...
enum	CAN_TX_FIFO_STATUS {   CAN_TX_FIFO_FULL = 0 , CAN_TX_FIFO_STATUS_MASK = 0x1F7 , CAN_TX_FIFO_NOT_FULL = 0x01 , CAN_TX_FIFO_HALF_FULL = 0x02 ,   CAN_TX_FIFO_EMPTY = 0x04 , CAN_TX_FIFO_ATTEMPTS_EXHAUSTED = 0x10 , CAN_TX_FIFO_ERROR = 0x20 , CAN_TX_FIFO_ARBITRATION_LOST = 0x40 ,   CAN_TX_FIFO_ABORTED = 0x80 , CAN_TX_FIFO_TRANSMITTING = 0x100 }
	CAN TX FIFO Status. More...
enum	CAN_TEF_FIFO_STATUS {   CAN_TEF_FIFO_EMPTY = 0 , CAN_TEF_FIFO_STATUS_MASK = 0x0F , CAN_TEF_FIFO_NOT_EMPTY = 0x01 , CAN_TEF_FIFO_HALF_FULL = 0x02 ,   CAN_TEF_FIFO_FULL = 0x04 , CAN_TEF_FIFO_OVERFLOW = 0x08 }
	CAN TEF FIFO Status. More...
enum	CAN_MODULE_EVENT {   CAN_NO_EVENT = 0 , CAN_ALL_EVENTS = 0xFF1F , CAN_TX_EVENT = 0x0001 , CAN_RX_EVENT = 0x0002 ,   CAN_TIME_BASE_COUNTER_EVENT = 0x0004 , CAN_OPERATION_MODE_CHANGE_EVENT = 0x0008 , CAN_TEF_EVENT = 0x0010 , CAN_RAM_ECC_EVENT = 0x0100 ,   CAN_SPI_CRC_EVENT = 0x0200 , CAN_TX_ATTEMPTS_EVENT = 0x0400 , CAN_RX_OVERFLOW_EVENT = 0x0800 , CAN_SYSTEM_ERROR_EVENT = 0x1000 ,   CAN_BUS_ERROR_EVENT = 0x2000 , CAN_BUS_WAKEUP_EVENT = 0x4000 , CAN_RX_INVALID_MESSAGE_EVENT = 0x8000 }
	CAN Module Event (Interrupts) More...
enum	CAN_TX_FIFO_EVENT {   CAN_TX_FIFO_NO_EVENT = 0 , CAN_TX_FIFO_ALL_EVENTS = 0x17 , CAN_TX_FIFO_NOT_FULL_EVENT = 0x01 , CAN_TX_FIFO_HALF_FULL_EVENT = 0x02 ,   CAN_TX_FIFO_EMPTY_EVENT = 0x04 , CAN_TX_FIFO_ATTEMPTS_EXHAUSTED_EVENT = 0x10 }
	CAN TX FIFO Event (Interrupts) More...
enum	CAN_RX_FIFO_EVENT {   CAN_RX_FIFO_NO_EVENT = 0 , CAN_RX_FIFO_ALL_EVENTS = 0x0F , CAN_RX_FIFO_NOT_EMPTY_EVENT = 0x01 , CAN_RX_FIFO_HALF_FULL_EVENT = 0x02 ,   CAN_RX_FIFO_FULL_EVENT = 0x04 , CAN_RX_FIFO_OVERFLOW_EVENT = 0x08 }
	CAN RX FIFO Event (Interrupts) More...
enum	CAN_TEF_FIFO_EVENT {   CAN_TEF_FIFO_NO_EVENT = 0 , CAN_TEF_FIFO_ALL_EVENTS = 0x0F , CAN_TEF_FIFO_NOT_EMPTY_EVENT = 0x01 , CAN_TEF_FIFO_HALF_FULL_EVENT = 0x02 ,   CAN_TEF_FIFO_FULL_EVENT = 0x04 , CAN_TEF_FIFO_OVERFLOW_EVENT = 0x08 }
	CAN TEF FIFO Event (Interrupts) More...
enum	CAN_SSP_MODE { CAN_SSP_MODE_OFF , CAN_SSP_MODE_MANUAL , CAN_SSP_MODE_AUTO }
	Secondary Sample Point Mode. More...
enum	CAN_ERROR_STATE {   CAN_ERROR_FREE_STATE = 0 , CAN_ERROR_ALL = 0x3F , CAN_TX_RX_WARNING_STATE = 0x01 , CAN_RX_WARNING_STATE = 0x02 ,   CAN_TX_WARNING_STATE = 0x04 , CAN_RX_BUS_PASSIVE_STATE = 0x08 , CAN_TX_BUS_PASSIVE_STATE = 0x10 , CAN_TX_BUS_OFF_STATE = 0x20 }
	CAN Error State. More...
enum	CAN_TS_MODE { CAN_TS_SOF = 0x00 , CAN_TS_EOF = 0x01 , CAN_TS_RES = 0x02 }
	CAN Time Stamp Mode Select. More...
enum	CAN_ECC_EVENT { CAN_ECC_NO_EVENT = 0x00 , CAN_ECC_ALL_EVENTS = 0x06 , CAN_ECC_SEC_EVENT = 0x02 , CAN_ECC_DED_EVENT = 0x04 }
	CAN ECC EVENT. More...
enum	CAN_CRC_EVENT { CAN_CRC_NO_EVENT = 0x00 , CAN_CRC_ALL_EVENTS = 0x03 , CAN_CRC_CRCERR_EVENT = 0x01 , CAN_CRC_FORMERR_EVENT = 0x02 }
	CAN CRC EVENT. More...
enum	GPIO_PIN_POS { GPIO_PIN_0 , GPIO_PIN_1 }
	GPIO Pin Position. More...
enum	GPIO_PIN_MODE { GPIO_MODE_INT , GPIO_MODE_GPIO }
	GPIO Pin Modes. More...
enum	GPIO_PIN_DIRECTION { GPIO_OUTPUT , GPIO_INPUT }
	GPIO Pin Directions. More...
enum	GPIO_OPEN_DRAIN_MODE { GPIO_PUSH_PULL , GPIO_OPEN_DRAIN }
	GPIO Open Drain Mode. More...
enum	GPIO_PIN_STATE { GPIO_LOW , GPIO_HIGH }
	GPIO Pin State. More...
enum	GPIO_CLKO_MODE { GPIO_CLKO_CLOCK , GPIO_CLKO_SOF }
	Clock Output Mode. More...
enum	CAN_TXREQ_CHANNEL {   CAN_TXREQ_CH0 = 0x00000001 , CAN_TXREQ_CH1 = 0x00000002 , CAN_TXREQ_CH2 = 0x00000004 , CAN_TXREQ_CH3 = 0x00000008 ,   CAN_TXREQ_CH4 = 0x00000010 , CAN_TXREQ_CH5 = 0x00000020 , CAN_TXREQ_CH6 = 0x00000040 , CAN_TXREQ_CH7 = 0x00000080 ,   CAN_TXREQ_CH8 = 0x00000100 , CAN_TXREQ_CH9 = 0x00000200 , CAN_TXREQ_CH10 = 0x00000400 , CAN_TXREQ_CH11 = 0x00000800 ,   CAN_TXREQ_CH12 = 0x00001000 , CAN_TXREQ_CH13 = 0x00002000 , CAN_TXREQ_CH14 = 0x00004000 , CAN_TXREQ_CH15 = 0x00008000 ,   CAN_TXREQ_CH16 = 0x00010000 , CAN_TXREQ_CH17 = 0x00020000 , CAN_TXREQ_CH18 = 0x00040000 , CAN_TXREQ_CH19 = 0x00080000 ,   CAN_TXREQ_CH20 = 0x00100000 , CAN_TXREQ_CH21 = 0x00200000 , CAN_TXREQ_CH22 = 0x00400000 , CAN_TXREQ_CH23 = 0x00800000 ,   CAN_TXREQ_CH24 = 0x01000000 , CAN_TXREQ_CH25 = 0x02000000 , CAN_TXREQ_CH26 = 0x04000000 , CAN_TXREQ_CH27 = 0x08000000 ,   CAN_TXREQ_CH28 = 0x10000000 , CAN_TXREQ_CH29 = 0x20000000 , CAN_TXREQ_CH30 = 0x40000000 , CAN_TXREQ_CH31 = 0x80000000 }
	TXREQ Channel Bits. More...
enum	CAN_ICODE {   CAN_ICODE_FIFO_CH0 , CAN_ICODE_FIFO_CH1 , CAN_ICODE_FIFO_CH2 , CAN_ICODE_FIFO_CH3 ,   CAN_ICODE_FIFO_CH4 , CAN_ICODE_FIFO_CH5 , CAN_ICODE_FIFO_CH6 , CAN_ICODE_FIFO_CH7 ,   CAN_ICODE_FIFO_CH8 , CAN_ICODE_FIFO_CH9 , CAN_ICODE_FIFO_CH10 , CAN_ICODE_FIFO_CH11 ,   CAN_ICODE_FIFO_CH12 , CAN_ICODE_FIFO_CH13 , CAN_ICODE_FIFO_CH14 , CAN_ICODE_FIFO_CH15 ,   CAN_ICODE_FIFO_CH16 , CAN_ICODE_FIFO_CH17 , CAN_ICODE_FIFO_CH18 , CAN_ICODE_FIFO_CH19 ,   CAN_ICODE_FIFO_CH20 , CAN_ICODE_FIFO_CH21 , CAN_ICODE_FIFO_CH22 , CAN_ICODE_FIFO_CH23 ,   CAN_ICODE_FIFO_CH24 , CAN_ICODE_FIFO_CH25 , CAN_ICODE_FIFO_CH26 , CAN_ICODE_FIFO_CH27 ,   CAN_ICODE_FIFO_CH28 , CAN_ICODE_FIFO_CH29 , CAN_ICODE_FIFO_CH30 , CAN_ICODE_FIFO_CH31 ,   CAN_ICODE_TOTAL_CHANNELS , CAN_ICODE_NO_INT = 0x40 , CAN_ICODE_CERRIF , CAN_ICODE_WAKIF ,   CAN_ICODE_RXOVIF , CAN_ICODE_ADDRERR_SERRIF , CAN_ICODE_MABOV_SERRIF , CAN_ICODE_TBCIF ,   CAN_ICODE_MODIF , CAN_ICODE_IVMIF , CAN_ICODE_TEFIF , CAN_ICODE_TXATIF ,   CAN_ICODE_RESERVED }
	ICODE. More...
enum	CAN_RXCODE {   CAN_RXCODE_FIFO_CH1 = 1 , CAN_RXCODE_FIFO_CH2 , CAN_RXCODE_FIFO_CH3 , CAN_RXCODE_FIFO_CH4 ,   CAN_RXCODE_FIFO_CH5 , CAN_RXCODE_FIFO_CH6 , CAN_RXCODE_FIFO_CH7 , CAN_RXCODE_FIFO_CH8 ,   CAN_RXCODE_FIFO_CH9 , CAN_RXCODE_FIFO_CH10 , CAN_RXCODE_FIFO_CH11 , CAN_RXCODE_FIFO_CH12 ,   CAN_RXCODE_FIFO_CH13 , CAN_RXCODE_FIFO_CH14 , CAN_RXCODE_FIFO_CH15 , CAN_RXCODE_FIFO_CH16 ,   CAN_RXCODE_FIFO_CH17 , CAN_RXCODE_FIFO_CH18 , CAN_RXCODE_FIFO_CH19 , CAN_RXCODE_FIFO_CH20 ,   CAN_RXCODE_FIFO_CH21 , CAN_RXCODE_FIFO_CH22 , CAN_RXCODE_FIFO_CH23 , CAN_RXCODE_FIFO_CH24 ,   CAN_RXCODE_FIFO_CH25 , CAN_RXCODE_FIFO_CH26 , CAN_RXCODE_FIFO_CH27 , CAN_RXCODE_FIFO_CH28 ,   CAN_RXCODE_FIFO_CH29 , CAN_RXCODE_FIFO_CH30 , CAN_RXCODE_FIFO_CH31 , CAN_RXCODE_TOTAL_CHANNELS ,   CAN_RXCODE_NO_INT = 0x40 , CAN_RXCODE_RESERVED }
	RXCODE. More...
enum	CAN_TXCODE {   CAN_TXCODE_FIFO_CH0 , CAN_TXCODE_FIFO_CH1 , CAN_TXCODE_FIFO_CH2 , CAN_TXCODE_FIFO_CH3 ,   CAN_TXCODE_FIFO_CH4 , CAN_TXCODE_FIFO_CH5 , CAN_TXCODE_FIFO_CH6 , CAN_TXCODE_FIFO_CH7 ,   CAN_TXCODE_FIFO_CH8 , CAN_TXCODE_FIFO_CH9 , CAN_TXCODE_FIFO_CH10 , CAN_TXCODE_FIFO_CH11 ,   CAN_TXCODE_FIFO_CH12 , CAN_TXCODE_FIFO_CH13 , CAN_TXCODE_FIFO_CH14 , CAN_TXCODE_FIFO_CH15 ,   CAN_TXCODE_FIFO_CH16 , CAN_TXCODE_FIFO_CH17 , CAN_TXCODE_FIFO_CH18 , CAN_TXCODE_FIFO_CH19 ,   CAN_TXCODE_FIFO_CH20 , CAN_TXCODE_FIFO_CH21 , CAN_TXCODE_FIFO_CH22 , CAN_TXCODE_FIFO_CH23 ,   CAN_TXCODE_FIFO_CH24 , CAN_TXCODE_FIFO_CH25 , CAN_TXCODE_FIFO_CH26 , CAN_TXCODE_FIFO_CH27 ,   CAN_TXCODE_FIFO_CH28 , CAN_TXCODE_FIFO_CH29 , CAN_TXCODE_FIFO_CH30 , CAN_TXCODE_FIFO_CH31 ,   CAN_TXCODE_TOTAL_CHANNELS , CAN_TXCODE_NO_INT = 0x40 , CAN_TXCODE_RESERVED }
	TXCODE. More...
enum	CAN_SYSCLK_SPEED { CAN_SYSCLK_40M = MCP2518FD_40MHz , CAN_SYSCLK_20M = MCP2518FD_20MHz , CAN_SYSCLK_10M = MCP2518FD_10MHz }
	System Clock Selection. More...
enum	OSC_CLKO_DIVIDE { OSC_CLKO_DIV1 , OSC_CLKO_DIV2 , OSC_CLKO_DIV4 , OSC_CLKO_DIV10 }
	CLKO Divide. More...

Variables
static const uint32_t	CAN_125K_500K = ( 4UL << 24) | (125000UL)
	CAN Bit Time Setup: Arbitration/Data Bit Phase.
static const uint32_t	CAN_250K_500K = ( 2UL << 24) | (250000UL)
static const uint32_t	CAN_250K_750K = ( 3UL << 24) | (250000UL)
static const uint32_t	CAN_250K_1M = ( 4UL << 24) | (250000UL)
static const uint32_t	CAN_250K_1M5 = ( 6UL << 24) | (250000UL)
static const uint32_t	CAN_250K_2M = ( 8UL << 24) | (250000UL)
static const uint32_t	CAN_250K_3M = (12UL << 24) | (250000UL)
static const uint32_t	CAN_250K_4M = (16UL << 24) | (250000UL)
static const uint32_t	CAN_500K_1M = ( 2UL << 24) | (500000UL)
static const uint32_t	CAN_500K_2M = ( 4UL << 24) | (500000UL)
static const uint32_t	CAN_500K_3M = ( 6UL << 24) | (500000UL)
static const uint32_t	CAN_500K_4M = ( 8UL << 24) | (500000UL)
static const uint32_t	CAN_500K_5M = (10UL << 24) | (500000UL)
static const uint32_t	CAN_500K_6M5 = (13UL << 24) | (500000UL)
static const uint32_t	CAN_500K_8M = (16UL << 24) | (500000UL)
static const uint32_t	CAN_500K_10M = (20UL << 24) | (500000UL)
static const uint32_t	CAN_1000K_4M = ( 4UL << 24) |(1000000UL)
static const uint32_t	CAN_1000K_8M = ( 8UL << 24) |(1000000UL)
static const uint32_t	canControlResetValues []
static const uint32_t	canFifoResetValues []
static const uint32_t	canFilterControlResetValue = 0x00000000
static const uint32_t	canFilterObjectResetValues [] = {0x00000000, 0x00000000}
static const uint32_t	mcp25xxfdControlResetValues []

Typedef Documentation

CAN_BUS_DIAG_FLAGS

typedef struct _CAN_BUS_DIAG_FLAGS CAN_BUS_DIAG_FLAGS

CAN Bus Diagnostic flags.

CAN_BUS_DIAGNOSTIC

typedef union _CAN_BUS_DIAGNOSTIC CAN_BUS_DIAGNOSTIC

CAN BUS DIAGNOSTICS.

CAN_BUS_ERROR_COUNT

typedef struct _CAN_BUS_ERROR_COUNT CAN_BUS_ERROR_COUNT

CAN Bus Diagnostic Error Counts.

CAN_CONFIG

typedef struct _CAN_CONFIG CAN_CONFIG

CAN Configure.

CAN_FILTEROBJ_ID

typedef struct _CAN_FILTEROBJ_ID CAN_FILTEROBJ_ID

CAN Filter Object ID.

CAN_INT_ENABLES

typedef struct _CAN_INT_ENABLES CAN_INT_ENABLES

Interrupt Enables.

CAN_INT_FLAGS

typedef struct _CAN_INT_FLAGS CAN_INT_FLAGS

Interrupt Flags.

CAN_MASKOBJ_ID

typedef struct _CAN_MASKOBJ_ID CAN_MASKOBJ_ID

CAN Mask Object ID.

CAN_MSG_TIMESTAMP

typedef uint32_t CAN_MSG_TIMESTAMP

CAN Message Time Stamp.

CAN_MSGOBJ_ID

typedef struct _CAN_MSGOBJ_ID CAN_MSGOBJ_ID

CAN Message Object ID.

CAN_OSC_CTRL

typedef struct _CAN_OSC_CTRL CAN_OSC_CTRL

Oscillator Control.

CAN_OSC_STATUS

typedef struct _CAN_OSC_STATUS CAN_OSC_STATUS

Oscillator Status.

CAN_RX_FIFO_CONFIG

typedef struct _CAN_RX_FIFO_CONFIG CAN_RX_FIFO_CONFIG

CAN Receive Channel Configure.

CAN_RX_MSGOBJ

typedef union _CAN_RX_MSGOBJ CAN_RX_MSGOBJ

CAN RX Message Object.

CAN_RX_MSGOBJ_CTRL

typedef struct _CAN_RX_MSGOBJ_CTRL CAN_RX_MSGOBJ_CTRL

CAN RX Message Object Control.

CAN_TEF_CONFIG

typedef struct _CAN_TEF_CONFIG CAN_TEF_CONFIG

CAN Transmit Event FIFO Configure.

CAN_TEF_MSGOBJ

typedef union _CAN_TEF_MSGOBJ CAN_TEF_MSGOBJ

CAN TEF Message Object.

CAN_TX_FIFO_CONFIG

typedef struct _CAN_TX_FIFO_CONFIG CAN_TX_FIFO_CONFIG

CAN Transmit Channel Configure.

CAN_TX_MSGOBJ

typedef union _CAN_TX_MSGOBJ CAN_TX_MSGOBJ

CAN TX Message Object.

CAN_TX_MSGOBJ_CTRL

typedef struct _CAN_TX_MSGOBJ_CTRL CAN_TX_MSGOBJ_CTRL

CAN TX Message Object Control.

CAN_TX_QUEUE_CONFIG

typedef struct _CAN_TX_QUEUE_CONFIG CAN_TX_QUEUE_CONFIG

CAN Transmit Queue Configure.

REG_CiBDIAG0

typedef union _REG_CiBDIAG0 REG_CiBDIAG0

Diagnostic Register 0.

REG_CiBDIAG1

typedef union _REG_CiBDIAG1 REG_CiBDIAG1

Diagnostic Register 1.

REG_CiCON

typedef union _REG_CiCON REG_CiCON

CAN Control Register.

REG_CiDBTCFG

typedef union _REG_CiDBTCFG REG_CiDBTCFG

Data Bit Time Configuration Register.

REG_CiFIFOCON

typedef union _REG_CiFIFOCON REG_CiFIFOCON

FIFO Control Register.

REG_CiFIFOSTA

typedef union _REG_CiFIFOSTA REG_CiFIFOSTA

FIFO Status Register.

REG_CiFIFOUA

typedef union _REG_CiFIFOUA REG_CiFIFOUA

FIFO User Address Register.

REG_CiFLTCON_BYTE

typedef union _REG_CiFLTCON_BYTE REG_CiFLTCON_BYTE

Filter Control Register.

REG_CiFLTOBJ

typedef union _REG_CiFLTOBJ REG_CiFLTOBJ

Filter Object Register.

REG_CiINT

typedef union _REG_CiINT REG_CiINT

Interrupt Register.

REG_CiINTENABLE

typedef union _REG_CiINTENABLE REG_CiINTENABLE

Interrupt Enable Register.

REG_CiINTFLAG

typedef union _REG_CiINTFLAG REG_CiINTFLAG

Interrupt Flag Register.

REG_CiMASK

typedef union _REG_CiMASK REG_CiMASK

Mask Object Register.

REG_CiNBTCFG

typedef union _REG_CiNBTCFG REG_CiNBTCFG

Nominal Bit Time Configuration Register.

REG_CiTDC

typedef union _REG_CiTDC REG_CiTDC

Transmitter Delay Compensation Register.

REG_CiTEFCON

typedef union _REG_CiTEFCON REG_CiTEFCON

Transmit Event FIFO Control Register.

REG_CiTEFSTA

typedef union _REG_CiTEFSTA REG_CiTEFSTA

Transmit Event FIFO Status Register.

REG_CiTREC

typedef union _REG_CiTREC REG_CiTREC

Transmit/Receive Error Count Register.

REG_CiTSCON

typedef union _REG_CiTSCON REG_CiTSCON

Time Stamp Configuration Register.

REG_CiTXQCON

typedef union _REG_CiTXQCON REG_CiTXQCON

Transmit Queue Control Register.

REG_CiTXQSTA

typedef union _REG_CiTXQSTA REG_CiTXQSTA

Transmit Queue Status Register.

REG_CiVEC

typedef union _REG_CiVEC REG_CiVEC

Interrupt Vector Register.

REG_CRC

typedef union _REG_CRC REG_CRC

CRC Regsiter.

REG_DEVID

typedef union _REG_DEVID REG_DEVID

DEVID Register.

REG_ECCCON

typedef union _REG_ECCCON REG_ECCCON

ECC Control Register.

REG_ECCSTA

typedef union _REG_ECCSTA REG_ECCSTA

ECC Status Register.

REG_IOCON

typedef union _REG_IOCON REG_IOCON

I/O Control Register.

REG_OSC

typedef union _REG_OSC REG_OSC

Oscillator Control Register.

REG_t

typedef union _REG_t REG_t

General 32-bit Register.

Enumeration Type Documentation

CAN_CRC_EVENT

enum CAN_CRC_EVENT

CAN CRC EVENT.

Enumerator
CAN_CRC_NO_EVENT
CAN_CRC_ALL_EVENTS
CAN_CRC_CRCERR_EVENT
CAN_CRC_FORMERR_EVENT

CAN_DLC

enum CAN_DLC

CAN Data Length Code.

Enumerator
CAN_DLC_0
CAN_DLC_1
CAN_DLC_2
CAN_DLC_3
CAN_DLC_4
CAN_DLC_5
CAN_DLC_6
CAN_DLC_7
CAN_DLC_8
CAN_DLC_12
CAN_DLC_16
CAN_DLC_20
CAN_DLC_24
CAN_DLC_32
CAN_DLC_48
CAN_DLC_64

CAN_DNET_FILTER_SIZE

enum CAN_DNET_FILTER_SIZE

Data Byte Filter Number.

Enumerator
CAN_DNET_FILTER_DISABLE
CAN_DNET_FILTER_SIZE_1_BIT
CAN_DNET_FILTER_SIZE_2_BIT
CAN_DNET_FILTER_SIZE_3_BIT
CAN_DNET_FILTER_SIZE_4_BIT
CAN_DNET_FILTER_SIZE_5_BIT
CAN_DNET_FILTER_SIZE_6_BIT
CAN_DNET_FILTER_SIZE_7_BIT
CAN_DNET_FILTER_SIZE_8_BIT
CAN_DNET_FILTER_SIZE_9_BIT
CAN_DNET_FILTER_SIZE_10_BIT
CAN_DNET_FILTER_SIZE_11_BIT
CAN_DNET_FILTER_SIZE_12_BIT
CAN_DNET_FILTER_SIZE_13_BIT
CAN_DNET_FILTER_SIZE_14_BIT
CAN_DNET_FILTER_SIZE_15_BIT
CAN_DNET_FILTER_SIZE_16_BIT
CAN_DNET_FILTER_SIZE_17_BIT
CAN_DNET_FILTER_SIZE_18_BIT

CAN_ECC_EVENT

enum CAN_ECC_EVENT

CAN ECC EVENT.

Enumerator
CAN_ECC_NO_EVENT
CAN_ECC_ALL_EVENTS
CAN_ECC_SEC_EVENT
CAN_ECC_DED_EVENT

CAN_ERROR_STATE

enum CAN_ERROR_STATE

CAN Error State.

Enumerator
CAN_ERROR_FREE_STATE
CAN_ERROR_ALL
CAN_TX_RX_WARNING_STATE
CAN_RX_WARNING_STATE
CAN_TX_WARNING_STATE
CAN_RX_BUS_PASSIVE_STATE
CAN_TX_BUS_PASSIVE_STATE
CAN_TX_BUS_OFF_STATE

CAN_FIFO_CHANNEL

enum CAN_FIFO_CHANNEL

CAN FIFO Channels.

Enumerator
CAN_FIFO_CH0
CAN_FIFO_CH1
CAN_FIFO_CH2
CAN_FIFO_CH3
CAN_FIFO_CH4
CAN_FIFO_CH5
CAN_FIFO_CH6
CAN_FIFO_CH7
CAN_FIFO_CH8
CAN_FIFO_CH9
CAN_FIFO_CH10
CAN_FIFO_CH11
CAN_FIFO_CH12
CAN_FIFO_CH13
CAN_FIFO_CH14
CAN_FIFO_CH15
CAN_FIFO_CH16
CAN_FIFO_CH17
CAN_FIFO_CH18
CAN_FIFO_CH19
CAN_FIFO_CH20
CAN_FIFO_CH21
CAN_FIFO_CH22
CAN_FIFO_CH23
CAN_FIFO_CH24
CAN_FIFO_CH25
CAN_FIFO_CH26
CAN_FIFO_CH27
CAN_FIFO_CH28
CAN_FIFO_CH29
CAN_FIFO_CH30
CAN_FIFO_CH31
CAN_FIFO_TOTAL_CHANNELS

CAN_FIFO_PLSIZE

enum CAN_FIFO_PLSIZE

FIFO Payload Size.

Enumerator
CAN_PLSIZE_8
CAN_PLSIZE_12
CAN_PLSIZE_16
CAN_PLSIZE_20
CAN_PLSIZE_24
CAN_PLSIZE_32
CAN_PLSIZE_48
CAN_PLSIZE_64

CAN_FILTER

enum CAN_FILTER

CAN Filter Channels.

Enumerator
CAN_FILTER0
CAN_FILTER1
CAN_FILTER2
CAN_FILTER3
CAN_FILTER4
CAN_FILTER5
CAN_FILTER6
CAN_FILTER7
CAN_FILTER8
CAN_FILTER9
CAN_FILTER10
CAN_FILTER11
CAN_FILTER12
CAN_FILTER13
CAN_FILTER14
CAN_FILTER15
CAN_FILTER16
CAN_FILTER17
CAN_FILTER18
CAN_FILTER19
CAN_FILTER20
CAN_FILTER21
CAN_FILTER22
CAN_FILTER23
CAN_FILTER24
CAN_FILTER25
CAN_FILTER26
CAN_FILTER27
CAN_FILTER28
CAN_FILTER29
CAN_FILTER30
CAN_FILTER31
CAN_FILTER_TOTAL

CAN_ICODE

enum CAN_ICODE

ICODE.

Enumerator
CAN_ICODE_FIFO_CH0
CAN_ICODE_FIFO_CH1
CAN_ICODE_FIFO_CH2
CAN_ICODE_FIFO_CH3
CAN_ICODE_FIFO_CH4
CAN_ICODE_FIFO_CH5
CAN_ICODE_FIFO_CH6
CAN_ICODE_FIFO_CH7
CAN_ICODE_FIFO_CH8
CAN_ICODE_FIFO_CH9
CAN_ICODE_FIFO_CH10
CAN_ICODE_FIFO_CH11
CAN_ICODE_FIFO_CH12
CAN_ICODE_FIFO_CH13
CAN_ICODE_FIFO_CH14
CAN_ICODE_FIFO_CH15
CAN_ICODE_FIFO_CH16
CAN_ICODE_FIFO_CH17
CAN_ICODE_FIFO_CH18
CAN_ICODE_FIFO_CH19
CAN_ICODE_FIFO_CH20
CAN_ICODE_FIFO_CH21
CAN_ICODE_FIFO_CH22
CAN_ICODE_FIFO_CH23
CAN_ICODE_FIFO_CH24
CAN_ICODE_FIFO_CH25
CAN_ICODE_FIFO_CH26
CAN_ICODE_FIFO_CH27
CAN_ICODE_FIFO_CH28
CAN_ICODE_FIFO_CH29
CAN_ICODE_FIFO_CH30
CAN_ICODE_FIFO_CH31
CAN_ICODE_TOTAL_CHANNELS
CAN_ICODE_NO_INT
CAN_ICODE_CERRIF
CAN_ICODE_WAKIF
CAN_ICODE_RXOVIF
CAN_ICODE_ADDRERR_SERRIF
CAN_ICODE_MABOV_SERRIF
CAN_ICODE_TBCIF
CAN_ICODE_MODIF
CAN_ICODE_IVMIF
CAN_ICODE_TEFIF
CAN_ICODE_TXATIF
CAN_ICODE_RESERVED

CAN_MODULE_EVENT

enum CAN_MODULE_EVENT

CAN Module Event (Interrupts)

Enumerator
CAN_NO_EVENT
CAN_ALL_EVENTS
CAN_TX_EVENT
CAN_RX_EVENT
CAN_TIME_BASE_COUNTER_EVENT
CAN_OPERATION_MODE_CHANGE_EVENT
CAN_TEF_EVENT
CAN_RAM_ECC_EVENT
CAN_SPI_CRC_EVENT
CAN_TX_ATTEMPTS_EVENT
CAN_RX_OVERFLOW_EVENT
CAN_SYSTEM_ERROR_EVENT
CAN_BUS_ERROR_EVENT
CAN_BUS_WAKEUP_EVENT
CAN_RX_INVALID_MESSAGE_EVENT

CAN_OPERATION_MODE

enum CAN_OPERATION_MODE

CAN Operation Modes.

Enumerator
CAN_NORMAL_MODE
CAN_SLEEP_MODE
CAN_INTERNAL_LOOPBACK_MODE
CAN_LISTEN_ONLY_MODE
CAN_CONFIGURATION_MODE
CAN_EXTERNAL_LOOPBACK_MODE
CAN_CLASSIC_MODE
CAN_RESTRICTED_MODE
CAN_INVALID_MODE

CAN_RX_FIFO_EVENT

enum CAN_RX_FIFO_EVENT

CAN RX FIFO Event (Interrupts)

Enumerator
CAN_RX_FIFO_NO_EVENT
CAN_RX_FIFO_ALL_EVENTS
CAN_RX_FIFO_NOT_EMPTY_EVENT
CAN_RX_FIFO_HALF_FULL_EVENT
CAN_RX_FIFO_FULL_EVENT
CAN_RX_FIFO_OVERFLOW_EVENT

CAN_RX_FIFO_STATUS

enum CAN_RX_FIFO_STATUS

CAN RX FIFO Status.

Enumerator
CAN_RX_FIFO_EMPTY
CAN_RX_FIFO_STATUS_MASK
CAN_RX_FIFO_NOT_EMPTY
CAN_RX_FIFO_HALF_FULL
CAN_RX_FIFO_FULL
CAN_RX_FIFO_OVERFLOW

CAN_RXCODE

enum CAN_RXCODE

RXCODE.

Enumerator
CAN_RXCODE_FIFO_CH1
CAN_RXCODE_FIFO_CH2
CAN_RXCODE_FIFO_CH3
CAN_RXCODE_FIFO_CH4
CAN_RXCODE_FIFO_CH5
CAN_RXCODE_FIFO_CH6
CAN_RXCODE_FIFO_CH7
CAN_RXCODE_FIFO_CH8
CAN_RXCODE_FIFO_CH9
CAN_RXCODE_FIFO_CH10
CAN_RXCODE_FIFO_CH11
CAN_RXCODE_FIFO_CH12
CAN_RXCODE_FIFO_CH13
CAN_RXCODE_FIFO_CH14
CAN_RXCODE_FIFO_CH15
CAN_RXCODE_FIFO_CH16
CAN_RXCODE_FIFO_CH17
CAN_RXCODE_FIFO_CH18
CAN_RXCODE_FIFO_CH19
CAN_RXCODE_FIFO_CH20
CAN_RXCODE_FIFO_CH21
CAN_RXCODE_FIFO_CH22
CAN_RXCODE_FIFO_CH23
CAN_RXCODE_FIFO_CH24
CAN_RXCODE_FIFO_CH25
CAN_RXCODE_FIFO_CH26
CAN_RXCODE_FIFO_CH27
CAN_RXCODE_FIFO_CH28
CAN_RXCODE_FIFO_CH29
CAN_RXCODE_FIFO_CH30
CAN_RXCODE_FIFO_CH31
CAN_RXCODE_TOTAL_CHANNELS
CAN_RXCODE_NO_INT
CAN_RXCODE_RESERVED

CAN_SSP_MODE

enum CAN_SSP_MODE

Secondary Sample Point Mode.

Enumerator
CAN_SSP_MODE_OFF
CAN_SSP_MODE_MANUAL
CAN_SSP_MODE_AUTO

CAN_SYSCLK_SPEED

enum CAN_SYSCLK_SPEED

System Clock Selection.

Enumerator
CAN_SYSCLK_40M
CAN_SYSCLK_20M
CAN_SYSCLK_10M

CAN_TEF_FIFO_EVENT

enum CAN_TEF_FIFO_EVENT

CAN TEF FIFO Event (Interrupts)

Enumerator
CAN_TEF_FIFO_NO_EVENT
CAN_TEF_FIFO_ALL_EVENTS
CAN_TEF_FIFO_NOT_EMPTY_EVENT
CAN_TEF_FIFO_HALF_FULL_EVENT
CAN_TEF_FIFO_FULL_EVENT
CAN_TEF_FIFO_OVERFLOW_EVENT

CAN_TEF_FIFO_STATUS

enum CAN_TEF_FIFO_STATUS

CAN TEF FIFO Status.

Enumerator
CAN_TEF_FIFO_EMPTY
CAN_TEF_FIFO_STATUS_MASK
CAN_TEF_FIFO_NOT_EMPTY
CAN_TEF_FIFO_HALF_FULL
CAN_TEF_FIFO_FULL
CAN_TEF_FIFO_OVERFLOW

CAN_TS_MODE

enum CAN_TS_MODE

CAN Time Stamp Mode Select.

Enumerator
CAN_TS_SOF
CAN_TS_EOF
CAN_TS_RES

CAN_TX_BANDWITH_SHARING

enum CAN_TX_BANDWITH_SHARING

Transmit Bandwidth Sharing.

Enumerator
CAN_TXBWS_NO_DELAY
CAN_TXBWS_2
CAN_TXBWS_4
CAN_TXBWS_8
CAN_TXBWS_16
CAN_TXBWS_32
CAN_TXBWS_64
CAN_TXBWS_128
CAN_TXBWS_256
CAN_TXBWS_512
CAN_TXBWS_1024
CAN_TXBWS_2048
CAN_TXBWS_4096

CAN_TX_FIFO_EVENT

enum CAN_TX_FIFO_EVENT

CAN TX FIFO Event (Interrupts)

Enumerator
CAN_TX_FIFO_NO_EVENT
CAN_TX_FIFO_ALL_EVENTS
CAN_TX_FIFO_NOT_FULL_EVENT
CAN_TX_FIFO_HALF_FULL_EVENT
CAN_TX_FIFO_EMPTY_EVENT
CAN_TX_FIFO_ATTEMPTS_EXHAUSTED_EVENT

CAN_TX_FIFO_STATUS

enum CAN_TX_FIFO_STATUS

CAN TX FIFO Status.

Enumerator
CAN_TX_FIFO_FULL
CAN_TX_FIFO_STATUS_MASK
CAN_TX_FIFO_NOT_FULL
CAN_TX_FIFO_HALF_FULL
CAN_TX_FIFO_EMPTY
CAN_TX_FIFO_ATTEMPTS_EXHAUSTED
CAN_TX_FIFO_ERROR
CAN_TX_FIFO_ARBITRATION_LOST
CAN_TX_FIFO_ABORTED
CAN_TX_FIFO_TRANSMITTING

CAN_TXCODE

enum CAN_TXCODE

TXCODE.

Enumerator
CAN_TXCODE_FIFO_CH0
CAN_TXCODE_FIFO_CH1
CAN_TXCODE_FIFO_CH2
CAN_TXCODE_FIFO_CH3
CAN_TXCODE_FIFO_CH4
CAN_TXCODE_FIFO_CH5
CAN_TXCODE_FIFO_CH6
CAN_TXCODE_FIFO_CH7
CAN_TXCODE_FIFO_CH8
CAN_TXCODE_FIFO_CH9
CAN_TXCODE_FIFO_CH10
CAN_TXCODE_FIFO_CH11
CAN_TXCODE_FIFO_CH12
CAN_TXCODE_FIFO_CH13
CAN_TXCODE_FIFO_CH14
CAN_TXCODE_FIFO_CH15
CAN_TXCODE_FIFO_CH16
CAN_TXCODE_FIFO_CH17
CAN_TXCODE_FIFO_CH18
CAN_TXCODE_FIFO_CH19
CAN_TXCODE_FIFO_CH20
CAN_TXCODE_FIFO_CH21
CAN_TXCODE_FIFO_CH22
CAN_TXCODE_FIFO_CH23
CAN_TXCODE_FIFO_CH24
CAN_TXCODE_FIFO_CH25
CAN_TXCODE_FIFO_CH26
CAN_TXCODE_FIFO_CH27
CAN_TXCODE_FIFO_CH28
CAN_TXCODE_FIFO_CH29
CAN_TXCODE_FIFO_CH30
CAN_TXCODE_FIFO_CH31
CAN_TXCODE_TOTAL_CHANNELS
CAN_TXCODE_NO_INT
CAN_TXCODE_RESERVED

CAN_TXREQ_CHANNEL

enum CAN_TXREQ_CHANNEL

TXREQ Channel Bits.

Enumerator
CAN_TXREQ_CH0
CAN_TXREQ_CH1
CAN_TXREQ_CH2
CAN_TXREQ_CH3
CAN_TXREQ_CH4
CAN_TXREQ_CH5
CAN_TXREQ_CH6
CAN_TXREQ_CH7
CAN_TXREQ_CH8
CAN_TXREQ_CH9
CAN_TXREQ_CH10
CAN_TXREQ_CH11
CAN_TXREQ_CH12
CAN_TXREQ_CH13
CAN_TXREQ_CH14
CAN_TXREQ_CH15
CAN_TXREQ_CH16
CAN_TXREQ_CH17
CAN_TXREQ_CH18
CAN_TXREQ_CH19
CAN_TXREQ_CH20
CAN_TXREQ_CH21
CAN_TXREQ_CH22
CAN_TXREQ_CH23
CAN_TXREQ_CH24
CAN_TXREQ_CH25
CAN_TXREQ_CH26
CAN_TXREQ_CH27
CAN_TXREQ_CH28
CAN_TXREQ_CH29
CAN_TXREQ_CH30
CAN_TXREQ_CH31

CAN_WAKEUP_FILTER_TIME

enum CAN_WAKEUP_FILTER_TIME

Wake-up Filter Time.

Enumerator
CAN_WFT00
CAN_WFT01
CAN_WFT10
CAN_WFT11

GPIO_CLKO_MODE

enum GPIO_CLKO_MODE

Clock Output Mode.

Enumerator
GPIO_CLKO_CLOCK
GPIO_CLKO_SOF

GPIO_OPEN_DRAIN_MODE

enum GPIO_OPEN_DRAIN_MODE

GPIO Open Drain Mode.

Enumerator
GPIO_PUSH_PULL
GPIO_OPEN_DRAIN

GPIO_PIN_DIRECTION

enum GPIO_PIN_DIRECTION

GPIO Pin Directions.

Enumerator
GPIO_OUTPUT
GPIO_INPUT

GPIO_PIN_MODE

enum GPIO_PIN_MODE

GPIO Pin Modes.

Enumerator
GPIO_MODE_INT
GPIO_MODE_GPIO

GPIO_PIN_POS

enum GPIO_PIN_POS

GPIO Pin Position.

Enumerator
GPIO_PIN_0
GPIO_PIN_1

GPIO_PIN_STATE

enum GPIO_PIN_STATE

GPIO Pin State.

Enumerator
GPIO_LOW
GPIO_HIGH

OSC_CLKO_DIVIDE

enum OSC_CLKO_DIVIDE

CLKO Divide.

Enumerator
OSC_CLKO_DIV1
OSC_CLKO_DIV2
OSC_CLKO_DIV4
OSC_CLKO_DIV10

Variable Documentation

CAN_1000K_4M

const uint32_t CAN_1000K_4M = ( 4UL << 24) |(1000000UL)

static

CAN_1000K_8M

const uint32_t CAN_1000K_8M = ( 8UL << 24) |(1000000UL)

static

CAN_125K_500K

const uint32_t CAN_125K_500K = ( 4UL << 24) | (125000UL)

static

CAN Bit Time Setup: Arbitration/Data Bit Phase.

CAN_250K_1M

const uint32_t CAN_250K_1M = ( 4UL << 24) | (250000UL)

static

CAN_250K_1M5

const uint32_t CAN_250K_1M5 = ( 6UL << 24) | (250000UL)

static

CAN_250K_2M

const uint32_t CAN_250K_2M = ( 8UL << 24) | (250000UL)

static

CAN_250K_3M

const uint32_t CAN_250K_3M = (12UL << 24) | (250000UL)

static

CAN_250K_4M

const uint32_t CAN_250K_4M = (16UL << 24) | (250000UL)

static

CAN_250K_500K

const uint32_t CAN_250K_500K = ( 2UL << 24) | (250000UL)

static

CAN_250K_750K

const uint32_t CAN_250K_750K = ( 3UL << 24) | (250000UL)

static

CAN_500K_10M

const uint32_t CAN_500K_10M = (20UL << 24) | (500000UL)

static

CAN_500K_1M

const uint32_t CAN_500K_1M = ( 2UL << 24) | (500000UL)

static

CAN_500K_2M

const uint32_t CAN_500K_2M = ( 4UL << 24) | (500000UL)

static

CAN_500K_3M

const uint32_t CAN_500K_3M = ( 6UL << 24) | (500000UL)

static

CAN_500K_4M

const uint32_t CAN_500K_4M = ( 8UL << 24) | (500000UL)

static

CAN_500K_5M

const uint32_t CAN_500K_5M = (10UL << 24) | (500000UL)

static

CAN_500K_6M5

const uint32_t CAN_500K_6M5 = (13UL << 24) | (500000UL)

static

CAN_500K_8M

const uint32_t CAN_500K_8M = (16UL << 24) | (500000UL)

static

canControlResetValues

const uint32_t canControlResetValues[]

static

Initial value:

= {
    
    0x04980760, 0x003E0F0F, 0x000E0303, 0x00021000,
    
    0x00000000, 0x00000000, 0x40400040, 0x00000000,
    
    0x00000000, 0x00000000, 0x00000000, 0x00000000,
    
    0x00000000, 0x00200000, 0x00000000, 0x00000000,
    
    0x00000400, 0x00000000, 0x00000000, 0x00000000}

canFifoResetValues

const uint32_t canFifoResetValues[]

static

Initial value:

= {0x00600400, 0x00000000,
                                              0x00000000}

canFilterControlResetValue

const uint32_t canFilterControlResetValue = 0x00000000

static

canFilterObjectResetValues

const uint32_t canFilterObjectResetValues[] = {0x00000000, 0x00000000}

static

mcp25xxfdControlResetValues

const uint32_t mcp25xxfdControlResetValues[]

static

Initial value:

= {
    0x00000460, 0x00000003, 0x00000000, 0x00000000, 0x00000000}